View SC1162_5584115.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

programmable synchronous dc/dc converter with low dropout regulator controller SC1162/3 ? 1999 semtech corp. october 25, 1999 652 mitchell road newbury park ca 91320 1 ordering information description the SC1162/3 combines a synchronous voltage mode controller with a low-dropout linear regulator providing most of the circuitry necessary to implement two dc/ dc converters for powering advanced microprocessors such as pentium ? ii. the SC1162/3 switching section features an integrated 5 bit d/a converter, pulse by pulse current limiting, integrated power good signaling, and logic compatible shutdown. the SC1162/3 switching section operates at a fixed frequency of 200khz, providing an optimum compromise between size, efficiency and cost in the intended application areas. the integrated d/a con- verter provides programmability of output voltage from 2.0v to 3.5v in 100mv increments and 1.30v to 2.05v in 50mv increments with no external components. the SC1162/3 linear section is a high performance positive voltage regulator design for either the gtl bus supply at 1.5v (SC1162) or an adjustable output (sc1163). the output of the linear regulator can provide up to 5a or more with the appropriate external mosfet. pentium is a registered trademark of intel corporation pin configuration tel:805-498-2111 fax:805-498-3804 web:http:// www.semtech.com block diagram features ? synchronous design, enables no heatsink solution ? 95% efficiency (switching section) ? 5 bit dac for output programmability ? on chip power good function ? designed for intel pentium ? ii requirements ? 1.5v or adj. @ 1% for linear section ? 1.300v-2.05v 1.5%; 2.100v-3.500v 2% applications ? pentium ? ll or deschutes microprocessor supplies ? flexible motherboards ? 1.3v to 3.5v microprocessor supplies ? programmable dual power supplies part number (1) package linear voltage temp. range (t j ) SC1162csw so-24 1.5v 0 to 125c sc1163csw so-24 adj. 0 to 125c note: (1) add suffix ?tr? for tape and reel. top view (24 pin soic) ldov gate ldos pgndl dl bstl pgndh dh bsth en vcc cs+ cs- vid3 vid4 vid2 vid0 vid1 vosense pwrgood ovp vcc 70mv current limit 1.25 ref d/a & level shift and high side mosfet drive shut- down logic oscillator r s q shoot- thru control synchronous mosfet driver error amp agnd fet controller 1.265v ref open collectors vcc
programmable synchronous dc/dc converter with low dropout regulator controller SC1162/3 ? 1999 semtech corp. october 25, 1999 652 mitchell road newbury park ca 91320 2 electrical characteristics unless specified: v cc = 4.75v to 5.25v; gnd = p gnd = 0v; v osense = v o ; 0mv < (csp-csm) < 60mv; ldov = 11.4v to 12.6v; t a = 25 o c parameter conditions min typ max units switching section output voltage i o = 2a see note 1. supply voltage v cc 4.2 7 v supply current v cc = 5.0 8 15 ma load regulation i o = 0.8a to 15a 1 % line regulation 0.5 % minimum operating voltage 4.2 v current limit voltage 55 70 85 mv oscillator frequency 175 200 225 khz oscillator max duty cycle 90 95 % dh sink/source current bsth-dh = 4.5v, dh-pgndh = 2v 1a dl sink/source current bstl-dl = 4.5v, dl-pgndl = 2v 1a output voltage tempco 65 ppm/ o c gain (a ol )v osense to v o 35 db ovp threshold voltage 120 % ovp source current v ovp = 3.0v 10 ma power good threshold voltage 85 115 % dead time 50 100 ns linear section quiescent current ldov = 12v 5 ma output voltage (SC1162) 1.485 1.500 1.515 v reference voltage (sc1163) 1.252 1.265 1.278 v feedback pin bias current (sc1163) 10 ua gain (a ol ) ldos to gate 90 db load regulation i o = 0 to 8a (2) 0.3 % line regulation 0.3 % output impedance 200 ? parameter symbol maximum units v cc to gnd v in -0.3 to +7 v pgnd to gnd 1 v bst to gnd -0.3 to +15 v operating temperature range t a 0 to +70 c junction temperature range t j 0 to +125 c storage temperature range t stg -65 to +150 c lead temperature (soldering) 10 seconds t l 300 c thermal impedance junction to ambient ja 80 c/w thermal impedance junction to case jc 25 c/w absolute maximum ratings notes: (1) see output voltage table (2) in application circuit
programmable synchronous dc/dc converter with low dropout regulator controller SC1162/3 ? 1999 semtech corp. october 25, 1999 652 mitchell road newbury park ca 91320 3 note: (1) all logic level inputs and outputs are open collector ttl compatible. pin description pin pin name pin function 1 agnd small signal analog and digital ground 2 nc no connection 3 nc no connection 4 ldos sense input for ldo 5 vcc input voltage 6 ovp high signal out if v o >setpoint +20% 7 pwrgood (1) open collector logic output, high if v o within 10% of setpoint 8 cs- current sense input (negative) 9 cs+ current sense input (positive) 10 pgndh power ground for high side switch 11 dh high side driver output 12 pgndl power ground for low side switch 13 dl low side driver output 14 bstl supply for low side driver 15 bsth supply for high side driver 16 en (1) logic low shuts down the converter; high or open for normal operation. 17 vosense top end of internal feedback chain 18 vid4 (1) programming input (msb) 19 vid3 (1) programming input 20 vid2 (1) programming input 21 vid1 (1) programming input 22 vid0 (1) programming input (lsb) 23 ldov +12v for ldo section 24 gate gate drive output ldo top view (24 pin soic) agnd gate ldos nc vcc ovp pwrgood cs- cs+ pgndh dh pgndl 1 2 3 ldov 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 vosense en bsth bstl dl vid0 vid1 vid2 vid3 vid4 nc
programmable synchronous dc/dc converter with low dropout regulator controller SC1162/3 ? 1999 semtech corp. october 25, 1999 652 mitchell road newbury park ca 91320 4 output voltage unless specified: vcc = 5.00v; gnd = pgnd = 0v; vosense = v o ; 0mv < (csp-csm) < 60mv; t a = 25 o c parameter conditions vid 43210 min typ max units output voltage i o = 2a in application circuit 01111 1.281 1.300 1.320 01110 1.330 1.350 1.370 01101 1.379 1.400 1.421 01100 1.428 1.450 1.472 01011 1.478 1.500 1.523 01010 1.527 1.550 1.573 01001 1.576 1.600 1.624 01000 1.625 1.650 1.675 00111 1.675 1.700 1.726 00110 1.724 1.750 1.776 00101 1.773 1.800 1.827 00100 1.822 1.850 1.878 00011 1.872 1.900 1.929 00010 1.921 1.950 1.979 00001 1.970 2.000 2.030 00000 2.019 2.050 2.081 11111 1.960 2.000 2.040 11110 2.058 2.100 2.142 11101 2.156 2.200 2.244 11100 2.254 2.300 2.346 11011 2.352 2.400 2.448 11010 2.450 2.500 2.550 11001 2.548 2.600 2.652 11000 2.646 2.700 2.754 10111 2.744 2.800 2.856 10110 2.842 2.900 2.958 10101 2.940 3.000 3.060 10100 3.038 3.100 3.162 10011 3.136 3.200 3.264 10010 3.234 3.300 3.366 10001 3.332 3.400 3.468 10000 3.430 3.500 3.570
programmable synchronous dc/dc converter with low dropout regulator controller SC1162/3 ? 1999 semtech corp. october 25, 1999 652 mitchell road newbury park ca 91320 5 vcc_core vlin gnd vid0 vid1 vid2 vid3 vid4 12v 5v en ovp pwrgd 5v c1 0.1uf l1 4uh r4 5mohm c18 0.1uf + c14 1500uf + c15 1500uf + c16 1500uf + c17 1500uf + c3 1500uf + c2 1500uf r1 10 c13 0.1uf q2 buk556 q1 buk556 c5 0.1uf q3 buk556 + r17 100k + c12 330uf r5 2.32k u1 SC1162/3csw agnd 1 vcc 5 ovp 6 pwrgood 7 cs- 8 cs+ 9 pgndh 10 dh 11 bsth 15 en 16 vo sense 17 vid4 18 vid3 19 vid2 20 vid1 21 vid0 22 dl 13 pgndl 12 bstl 14 nc 24 gate 2 ldov 23 ldos 3 nc 4 r6 1.00k r12 r13 r16 10k notes: for SC1162, r12 and r13 are not required connect ldos (pin4) directly to vlin to generate 1.5v output. + c21 330uf * * * see "setting ldo output voltage" table r17 required if vinlin can be present without 12v being present application circuit
programmable synchronous dc/dc converter with low dropout regulator controller SC1162/3 ? 1999 semtech corp. october 25, 1999 652 mitchell road newbury park ca 91320 6 materials list qty. reference part/description vendor notes 4 c1,c5,c13,c 18 0.1f ceramic various 6 c2,c3,c14- c17 1500f/6.3v sanyo mv-gx or equiv. low esr 3 c11,c12, c21 330f/6.3v various 1 l1 4h 8 turns 16awg on micrometals t50-52d core 3 q1,q2,q3 see notes see notes fet selection requires trade-off between efficiency and cost. absolute maximum r ds(on) = 22 m ? for q1,q2 1r4 5m ? irc oar-1 series 1r5 2.32k ? , 1%, 1/8w various 1r6 1k ? , 1%, 1/8w various 1r1 10 ? , 5%, 1/8w various 1 r12 1%, 1/8w various see table (not required for SC1162) 1 r13 1%, 1/8w various see table (not required for SC1162) 1 r17 100k, 5%, 1/8w various required if voltage is applied to the linear fet without 12v applied to SC1162/3 1 u1 SC1162/3csw semtech setting ldo output voltage r b r a v o ldo r12 r13 3.45v 105 ? 182 ? 3.30v 105 ? 169 ? 3.10v 102 ? 147 ? 2.90v 100 ? 130 ? 2.80v 100 ? 121 ? 2.50v 100 ? 97.6 ? 1.50v 100 ? 18.7 ? error t significan cause not does term ) r i ( that the so enough low be must r and r ion clarificat for diagram layout see resistor feedback bottom r resistor feedback top r current bias pin feedback i : where ) r i ( r ) r r ( 265 . 1 v a fb b a b a fb a fb b b a out ? = = = ? + + ? =
programmable synchronous dc/dc converter with low dropout regulator controller SC1162/3 ? 1999 semtech corp. october 25, 1999 652 mitchell road newbury park ca 91320 7 70% 75% 80% 85% 90% 95% 0 2 4 6 8 10121416 io (amps) efficiency 3.5v std 3.5v sync 3.5v sync lo rds typical efficiency at vo=3.5v 70% 75% 80% 85% 90% 95% 0 2 4 6 8 10 12 14 16 io (amps) efficiency 2.5v std 2.5v sync 2.5v sync lo rds typical ripple, vo=2.8v, io=10a 70% 75% 80% 85% 90% 95% 0 2 4 6 8 10 12 14 16 io (amps) efficiency 2.8v std 2.8v sync 2.8v sync lo rds typical efficiency at vo=2.8v 70% 75% 80% 85% 90% 95% 0 2 4 6 8 10 12 14 16 io (amps) efficiency 2.0v std 2.0v sync 2.0v sync lo rds typical efficiency at vo=2.0v transient response vo=2.8v, io=300ma to 10a typical efficiency at vo=2.5v
programmable synchronous dc/dc converter with low dropout regulator controller SC1162/3 ? 1999 semtech corp. october 25, 1999 652 mitchell road newbury park ca 91320 8 layout guidelines careful attention to layout requirements are necessary for successful implementation of the SC1162/3 pwm controller. high currents switching at 200khz are pre- sent in the application and their effect on ground plane voltage differentials must be understood and mini- mized. 1). the high power parts of the circuit should be laid out first. a ground plane should be used, the number and position of ground plane interruptions should be such as to not unnecessarily compromise ground plane in- tegrity. isolated or semi-isolated areas of the ground plane may be deliberately introduced to constrain ground currents to particular areas, for example the in- put capacitor and bottom fet ground. 2). the loop formed by the input capacitor(s) (cin), the top fet (q1) and the bottom fet (q2) must be kept as small as possible. this loop contains all the high cur- rent, fast transition switching. connections should be as wide and as short as possible to minimize loop induc- tance. minimizing this loop area will a) reduce emi, b) lower ground injection currents, resulting in electrically ?cleaner? grounds for the rest of the system and c) mini- mize source ringing, resulting in more reliable gate switching signals. 3). the connection between the junction of q1, q2 and the output inductor should be a wide trace or copper region. it should be as short as practical. since this connection has fast voltage transitions, keeping this connection short will minimize emi. the connection be- tween the output inductor and the sense resistor should be a wide trace or copper area, there are no fast volt- age or current transitions in this connection and length is not so important, however adding unnecessary impedance will reduce efficiency. vout 12v in 5v vo lin 5v 4uh 5mohm + cout + cin 10 q2 0.1uf q3 + cout lin 2.32k 1.00k rb ra + cin lin SC1162/3 agnd 1 vcc 5 ovp 6 pwrgood 7 cs- 8 cs+ 9 pgndh 10 dh 11 bsth 15 en 16 vo sense 17 vid4 18 vid3 19 vid2 20 vid1 21 vid0 22 dl 13 pgndl 12 bstl 14 nc 24 gate 2 ldov 23 ldos 3 nc 4 q1 0.1uf heavy lines indicate high current paths. are not required. ldos connects to for SC1162, ra and rb vo lin layout diagram for the SC1162/3
programmable synchronous dc/dc converter with low dropout regulator controller SC1162/3 ? 1999 semtech corp. october 25, 1999 652 mitchell road newbury park ca 91320 9 vout 5v + + 4) the output capacitor(s) (cout) should be located as close to the load as possible, fast transient load currents are supplied by cout only, and connections between cout and the load must be short, wide cop- per areas to minimize inductance and resistance. 5) the SC1162/3 is best placed over a quite ground plane area, avoid pulse currents in the cin, q1, q2 loop flowing in this area. pgndh and pgndl should be returned to the ground plane close to the package. the agnd pin should be connected to the ground side of (one of) the output capacitor(s). if this is not possible, the agnd pin may be connected to the ground path between the output capacitor(s) and the cin, q1, q2 loop. under no circumstances should agnd be returned to a ground inside the cin, q1, q2 loop. 6) vcc for the SC1162/3 should be supplied from the 5v supply through a 10 ? resistor, the vcc pin should be decoupled directly to agnd by a 0.1 f ceramic capacitor, trace lengths should be as short as possi- ble. 7) the current sense resistor and the divider across it should form as small a loop as possible, the traces running back to cs+ and cs- on the SC1162/3 should run parallel and close to each other. the 0.1 f ca- pacitor should be mounted as close to the cs+ and cs- pins as possible. 8) ideally, the ground for the ldo section should be returned to the ground side of (one of) the switching section output capacitor(s). currents in various parts of the power section
programmable synchronous dc/dc converter with low dropout regulator controller SC1162/3 ? 1999 semtech corp. october 25, 1999 652 mitchell road newbury park ca 91320 10 component selection switching section output capacitors - selection begins with the most critical component. because of fast transient load current requirements in modern microprocessor core supplies, the output capacitors must supply all transient load current requirements until the current in the output inductor ramps up to the new level. output capacitor esr is therefore one of the most important criteria. the maximum esr can be simply calculated from: step current transient excursion voltage transient maximum where = = t t t t esr i v i v r each capacitor total technology c (f) esr (m ? ) qty. rqd. c (f) esr (m ? ) low esr tantalum 330 60 6 2000 10 os-con 330 25 3 990 8.3 low esr aluminum 1500 44 5 7500 8.8 () o in t esr v v i c r l ? osc in l f l v i ripple ? ? = 4 in o on ds o cond v v r i p ? ? = cycle duty = where ) ( 2 2 10 ? ? ? = in o sw v i p 4 ) ( osc f r in o sw f t t v i p ? + ? ? = osc in rr rr f v q p ? ? = for example, to meet a 100mv transient limit with a 10a load step, the output capacitor esr must be less than 10m ? . to meet this kind of esr level, there are three available capacitor technologies: the choice of which to use is simply a cost /perfor- mance issue, with low esr aluminum being the cheapest, but taking up the most space. inductor - having decided on a suitable type and value of output capacitor, the maximum allowable value of inductor can be calculated. too large an in- ductor will produce a slow current ramp rate and will cause the output capacitor to supply more of the tran- sient load current for longer - leading to an output volt- age sag below the esr excursion calculated above. the maximum inductor value may be calculated from: the calculated maximum inductor value assumes 100% duty cycle, so some allowance must be made. choosing an inductor value of 50 to 75% of the calculated maxi- mum will guarantee that the inductor current will ramp fast enough to reduce the voltage dropped across the esr at a faster rate than the capacitor sags, hence en- suring a good recovery from transient with no additional excursions. we must also be concerned with ripple current in the output inductor and a general rule of thumb has been to allow 10% of maximum output current as ripple current. note that most of the output voltage ripple is produced by the inductor ripple current flowing in the output capac- itor esr. ripple current can be calculated from: ripple current allowance will define the minimum permit- ted inductor value. power fets - the fets are chosen based on several criteria with probably the most important being power dissipation and power handling capability. top fet - the power dissipation in the top fet is a combination of conduction losses, switching losses and bottom fet body diode recovery losses. a) conduction losses are simply calculated as: b) switching losses can be estimated by assuming a switching time, if we assume 100ns then: or more generally, c) body diode recovery losses are more difficult to esti- mate, but to a first approximation, it is reasonable to as- sume that the stored charge on the bottom fet body diode will be moved through the top fet as it starts to turn on. the resulting power dissipation in the top fet will be: to a first order approximation, it is convenient to only consider conduction losses to determine fet suitability. for a 5v in; 2.8v out at 14.2a requirement, typical fet losses would be:
programmable synchronous dc/dc converter with low dropout regulator controller SC1162/3 ? 1999 semtech corp. october 25, 1999 652 mitchell road newbury park ca 91320 11 fet type r ds(on) (m ? ) p d (w) package buk556h 22 2.48 to220 irl2203 7.0 0.79 d 2 pak si4410 13.5 1.53 so-8 ) 1 ( ) ( 2 ? ? ? = on ds o cond r i p fet type r ds(on) (m ? ) p d (w) package buk556h 22 1.95 to220 irl2203 7.0 0.62 d 2 pak si4410 13.5 1.20 so-8 bottom fet - bottom fet losses are almost entirely due to conduction. the body diode is forced into conduc- tion at the beginning and end of the bottom switch con- duction period, so when the fet turns on and off, there is very little voltage across it, resulting in low switching losses. conduction losses for the fet can be deter- mined by: for the example above: each of the package types has a characteristic thermal impedance, for the to-220 package, thermal impedance is mostly determined by the heatsink used. for the sur- face mount packages on double sided fr4, 2 oz printed circuit board material, thermal impedances of 40 o c/w for the d 2 pak and 80 o c/w for the so-8 are readily achievable. the corresponding temperature rise is de- tailed below: temperature rise ( o c) fet type top fet bottom fet buk556h 49.6 (1) 39.0 (1) irl2203 31.6 24.8 si4410 122.4 96 (1) with 20 o c/w heatsink it is apparent that single so-8 si4410 are not adequate for this application, but by using parallel pairs in each posi- tion, power dissipation will be approximately halved and temperature rise reduced by a factor of 4. input capacitors - since the rms ripple current in the input capacitors may be as high as 50% of the out- put current, suitable capacitors must be chosen ac- cordingly. also, during fast load transients, there may be restrictions on input di/dt. these restrictions require useable energy storage within the converter circuitry, either as extra output capacitance or, more usually, additional input capacitors. choosing low esr input capacitors will help maximize ripple rating for a given size.
programmable synchronous dc/dc converter with low dropout regulator controller SC1162/3 ? 1999 semtech corp. october 25, 1999 652 mitchell road newbury park ca 91320 12 outline drawing jedec ms-013ad b17104b ecn99-667

▲Up To Search▲

Price & Availability of SC1162

	To Download SC1162 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .